(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming self-aligned polysilicon gate field effect transistors.
(2) Background to the Invention and Description of Related Art
Complimentary metal oxide semiconductor(CMOS) field effect transistor(FET) technology involves the formation n-channel FETs(NMOS) and p-channel FETs(PMOS) in combination to form low current, high performance integrated circuits. The complimentary use of NMOS and PMOS devices, typically in the form of a basic inverter device, allows a considerable increase of circuit density of circuit elements by reduction of heat generation. The increase in device density accompanied by the shrinkage of device size has resulted in improved circuit performance and reliability as well as reduced cost. For these reasons CMOS integrated circuits have found widespread use, particularly in digital applications.
The basic MOSFET (Metal Oxide Semiconductor Field Effect Transistor), whether it be an NMOS or PMOS is typically formed by a self-aligned polysilicon gate process wherein source and drain regions are formed adjacent to the polysilicon gate by ion implantation using the gate as a mask. The source/drain is thereby self-aligned to the gate electrode. A channel region directly under the polysilicon gate is thereby also defined by the gate electrode. In order to reduce hot electron injection into the channel region, a low concentration of source/drain dopant is first implanted with the gate as a mask. This is commonly referred to as a lightly doped drain (LDD) implant. Sidewalls are then formed alongside the gate electrode and a second substantially higher dosage implant is then applied to form the main source/drain regions which are spaced laterally away from the edge of the polysilicon gate by the sidewall thickness. The completed source/drain regions then each consist of a main heavily doped portion to which external contact is made and a lightly doped (LDD) portion next to the channel region.
As device dimension continue to shrink, short channel effects become significant and begin to affect device performance. In conventional LDD processes short channel effects are compensated by implanting shallower junctions which come at the expense of high impurity concentrations. As a consequence, the resultant lower impurity concentrations cause undesirably high source and drain series resistance. It would be beneficial to be able to form shallow LDD regions with high impurity concentration. The process of the present invention, which introduces LDD dopant from a silicon spacer, overcomes these shortcomings which are characteristic of ion implanted LDD regions.
Diffusion of dopants into active regions, in particular LDD regions, using a polysilicon spacer as a dopant source is not new. However the method of the present invention overcomes some of the shortcomings of the prior methods. Wu, U.S. Pat. No. 6,136,636 discloses a method for simultaneously forming source/drain and LDD regions by ion implanting dopant ions into a substrate where the LDD regions are covered by an amorphous silicon layer on a pad oxide. The source/drain regions are uncovered and therefore receive a greater dose than the covered LDD regions. The amorphous silicon layer is then oxidized and the dopant implanted therein is driven into the substrate through the subjacent pad oxide. The pad oxide also forms a sidewall on the polysilicon gate. Thus the pad oxide sidewall determines the final spacing of the LDD edge with respect to the edge of the gate electrode. There are several disadvantages of this technique. One disadvantage is that the final spacing of the LDD edge and the LDD diffusion are both dependent upon the pad oxide thickness and thereby also upon each other. Although shallow LDD regions may be formed by this method, the dopant concentration and profile is nevertheless determined by the non-uniform implanted dopant profile which is further dispersed after transit through the pad oxide resulting in a weakened or less abrupt dopant profile. In addition, the segregation coefficients of the dopants between oxide and silicon are different forxe2x80x94and p-type dopants.
In a related patent, Wu, U.S. Pat. No. 5,930,617 diffuses nitrogen from an amorphous silicon layer (not a sidewall) through an intermediate pad oxide to form shallow LDD regions. The diffusion takes place concurrently with the oxidation of the amorphous layer. While slightly different than Wu ""636, the method suffers from the same disadvantages cited above.
Gardner, et.al., U.S. Pat. No. 5,710,054 shows a method for diffusing shallow LDD regions from doped polysilicon spacers wherein the spacers are separated from the main polysilicon gate electrode by an oxide spacer which is thermally grown on the gate electrode. Not only is the oxide spacer difficult to form because it is trimmed by wet etching, but also the structure is subject to gate-to-source/drain shorts/leakage from the lower edge of the polysilicon gate to the polysilicon spacer. Further, if contacts are later formed by a salicide process, gate-to-source drain shorts are likely to occur by silicide bridging over the thin oxide from the upper edge of the gate electrode to the polysilicon sidewall. In another embodiment of the same reference an oxide sidewall spacer is formed, using conventional spacer formation methodology, alongside the gate electrode to control the lateral diffusion from the polysilicon sidewall source towards the channel region. This conventional spacer presents a high risk of silicide bridging during contact formation because of it""s narrow upper section.
Son, U.S. Pat. No. 5,759,885 shows the formation of a CMOS structure wherein n-type LDD regions are formed for both the n-channel and p-channel devices by diffusing phosphorous from doped polysilicon spacers into the silicon substrate through an intermediate oxide layer. The p-type source/drain regions of the p-channel device are formed by out diffusion from a blanket BSG (borosilicate glass) layer. Like Wu, the method of Son has the disadvantages of diffusing LDD dopant through an intermediate oxide.
It is an object of this invention to provide a method for forming shallow LDD diffusions.
It is another object of this invention to provide a method for forming a CMOS having shallow p-type LDD elements on the p-channel device.
It is yet another object of this invention to provide a method for forming an ultra narrow diffusion source which is in direct contact with the subjacent silicon which is to be the diffusion recipient.
It is still another object of this invention to provide a method for forming an ultra narrow silicon diffusion source positioned alongside a polysilicon gate electrode and spaced therefrom by an essentially rectangular dielectric spacer.
It is still another object of this invention to provide a method for forming an ultra shallow, high concentration diffused element in a silicon substrate.
It is another object of this invention to provide a method for reducing source/drain series resistance of a polysilicon gate MOSFET.
It is another object of this invention to provide a method for reducing lateral encroachment of boron dopant under the gate of a p-channel MOSFET.
It is another object of this invention to provide a method for reducing short channel effects in a p-channel MOSFET.
It is yet another object of this invention to provide a method for reducing gate-to-source/drain shorts in MOSFETs formed by a salicide process.
It is still another object of this invention to provide a method for forming a source/drain contact which is made to both to the single crystalline silicon of the main source/drain region but also to the LDD region.
These objects are accomplished by forming essentially rectangular silicon nitride sidewalls alongside a polysilicon gate stack. The gate stack comprises a gate oxide, a polysilicon gate over the gate oxide and a silicon oxide top cap. The silicon nitride sidewall spacer is made essentially rectangular by a CMP (chemical mechanical planarization) and etching process.
Amorphous silicon sidewalls are then formed alongside the nitride sidewalls by conventional sidewall practices wherein a blanket silicon layer is deposited. The layer is then anisotropically etched leaving a silicon sidewall which is spaced laterally away from the polysilicon gate by the thickness of the nitride spacer. The silicon sidewalls, after implantation with dopant ions, serves as a diffusion source to form an LDD region in the subjacent active single crystalline silicon. A combination of furnace and rapid thermal annealing (RTA) is then used to drive the implanted dopant into the silicon surface and crystallizing and activating the silicon sidewall. Because the diffusion source is in direct contact with the active silicon, the LDD regions can be made shallow and the junctions abrupt. Such a junctions result in improved device performance and are relatively immune to short channel effects as compared to conventionally formed LDD junctions. In addition, there is less encroachment of the shallow LDD region under the gate electrode.
LDD junctions formed using the silicon source according to the teaching of this invention are shallower and permit higher drive currents than those formed using conventional BSG sources. While LDD diffusion from a BSG source results in much less tailing than conventional ion implantation, the tailing from the doped silicon source outlined in this invention is even less than that from the BSG source. This results in a more abrupt junction and still higher performance.